1. Field of the Invention
The present invention relates to methods for making closely coupled closely aligned stacked integrated electronic circuits, optical circuits and MEMS. In particular, the present invention relates to methods specific to fabrication integration, yield enhancement, performance enhancement, power dissipation reduction and cost reduction.
2. State of the Art
Manufacturing Integrated Circuit [IC] methods are most notable for an exponential rate in the integration progression of electronic devices per unit area, consistently doubling approximately every 18 months over a short forty year history. These manufacturing methods are remarkable for their abilities of increasing circuit performance while simultaneously reducing circuit cost, power and size, and as a result ICs have contributed in no small measure to today's modern way of life.
The integration progression has repeatedly enabled the making of ICs that were not possible or practical only a few years earlier. What before prevented the practical implementation of circuits with 100,000 transistors due to excessive power dissipation or low fabrication yields, the integration progression has now enabled practical yields of circuits with 100,000,000 transistors and at much lower power dissipations despite the dramatic increase in transistor count. The integration progression has made possible the expectation that ICs with more than 1 billion transistors will be in wide spread common use within the next three to four years.
The ultimate and widely understood objective of the IC integration progression is to reduce all electronic systems or subsystems composed of multiple ICs to one IC. This ultimate IC is often commonly referred to as a SoC [System on Chip]. The result of this objective is ever lower cost of manufacturing, higher performance, and hopefully therefore, a greater end user utility and social benefit. FIG. 1 shows in cross section a conventional planar IC composed of number of IP [Intellectual Property] circuit blocks 1a which are interconnected by numerous layers of horizontal metal interconnect or wiring 1b. 
Electronic systems and subsystems made from assemblies of separate planar ICs are performance or cost reduction limited foremost by the implementation means for off-circuit or off-chip interconnections or I/Os. The performance and cost reduction limitations due to IC I/O result from manufacturing restrictions in the number of I/Os an IC may have, the cost of packaging, the significantly lower transmission performance of off-circuit connections versus on-circuit connections and the higher power dissipation required for off-chip signal transmission. Further, there is not presently planar IC fabrication technology that will allow the integration onto one planar IC for all of the significantly different IC fabrication processes used to make the electronic components of widely used products such as PCs, PDAs or cell phones. This is likely to remain so for the foreseeable future, because past demand for greater capabilities from such electronic products has resulted in greater divergence of the IC fabrication processes used to implement the various types of ICs from which they are made.
The usefulness of the integration progression is now strongly challenged by the growing complexity in the design, and logical and physical verification development and test efforts required to bring ICs to market. The wide spread incorporation of previously designed or off the shelf logic functions referred to as IP [Intellectual Property] is an example of efforts being taken to address IC design and development complexity. However, the usage of ever greater numbers of IP placements across an IC has resulted in greater logical, physical and manufacturing interconnection complexity.
The integration progression rate has changed the relationship of the primary cost structure components for making ICs. The cost of testing ICs is now approaching and in a number of cases exceeding IC fabrication cost and the cost of IC packaging ranging from 25% to several times IC fabrication cost. The cost dominance of test and packaging over IC fabrication increases with each generation of IC fabrication technology. It is becoming clear that IC manufacturing methods that reduce through IC integration techniques the cost of test and packaging are of most importance.
The integration progression is presently challenged by the need for methods to integrate as a single die not only active electronics, but also passive electronic devices, optical devices and MEMS [Micro-Electro-Mechanical Systems]. This need is particularly evident in networking and telecommunication equipment where the switching of optical signals through the conversion of optical signals to electronic and back, to optical or electronically controlled MEMS of optical mirrors are used. But also in consumer products such as video devices that use imaging arrays which need higher integration of processing electronics and memory or wireless communication devices which need greater integration of analog and passive circuitry.
The primary drivers of the integration progression of planar IC manufacturing have been circuit feature size reduction through fabrication process methods and increased wafer or substrate diameter. Volume production process fabrication methods for the dominate CMOS semiconductor technology has presently reached feature sizes of 0.12 μm [120 nm], and wafer sizes of 300 mm [12 inches]. Methods for forming stacked ICs or stacked IC structures have been demonstrated and are expected to become one more of the primary drivers of the IC integration progression.
IC stacking methods can be broadly classified as:                1. Package driven stacked ICs.        2. Process driven [design and fabrication] stacked closely coupled ICs.        
The stacking of ICs through various packaging methods or package driven stacking has a long and varied application history that goes back at least twenty years. A recent article published in the IEEE Spectrum entitled “Packages Go Vertical” by Harry Goldstein, August 2001, pages 46-51, is one representative summary of the more recent methods of 3D packaging of Integrated Circuits. The primary benefit of package driven stacking of ICs is reduced physical volume, implemented through the use of conventional ICs with various methods of forming peripheral connections from the I/O contacts of each IC to a common set of termination contacts of the package envelop enclosing the ICs.
The stacking of ICs through process drive methods, typically requires custom designed ICs and wafer level processing steps. The primary benefits of process driven IC stacking are increased performance with simultaneous reductions of cost, size and power. Process driven stacked ICs can be generally characterized by the following process steps:                1. Wafer level bonding with a bonding material thickness of a few microns or less.        2. Thinning of wafer circuit layers to less than 50 μm and typically less than 25 μm and less than 15 μm.        3. Vertical through the circuit layer substrate interconnections or interconnections that are internal to the IC stack.        
Process driven wafer stacking fabrication in the above manner will herein also be referred to as Closely Coupled stacked integrated circuits. The Closely Coupled stacked integrated circuit layers of the invention herein are thinned to facilitate the fabrication of fine grain vertical interconnections passing through the circuit layers and substantially flexible, and wherein these layers are preferably fabricated using low stress or stress controlled dielectric materials. The primary objective of closely coupled wafer stacking is to enhance the integration progression of IC fabrication beyond that possible with existing planar wafer process fabrication methods and wafer diameter. Closely coupled stacked IC prior art by the inventor and referred to as 3DS [Three Dimensional Structures] are U.S. Pat. Nos. 5,915,167, 6,208,545, 6,133,640, 6,551,857, 6,563,224, 5,985,693 and 5,654,220.
Closely coupled wafer bonding requires wafer to wafer alignment prior to bonding. Equipment presently available has the capability for ±1 μm wafer to wafer alignment. By comparison horizontal interconnection minimum pitch is 0.15 μm [150 nm] with current state of the art semiconductor processes. The horizontal routing efficiency through vertical interconnections is determined by wafer to wafer alignment, and is fundamentally important to the scaling of fine grain vertical interconnections to maintain compatibly with reducing horizontal interconnection geometries.
The state of the art for completed or fabricated planar ICs has and presently results in the expectation that the utility of a fabricated IC does not allow its reuse for subsequent IC integration in a single die or single IC. This is to say that subsequent integration of post-fabricated planar semiconductor circuitry with other fabricated ICs that would result in device and interconnection integration densities that are the same or similar to any of the planar ICs being integrated, and therefore, providing the well known attendant benefits of single IC integration, is no longer possible. Therefore, any and all subsequent circuit design changes or additions [placement of circuitry or horizontal interconnect routing layers] to a completed planar IC requires the IC be remade, requiring at a minimum revalidation of electrical and functional operation of the circuit, the remaking of mask tooling, circuit fabrication and in most cases the obsolescence of previous circuit inventory. This is a clear and significant restriction on the control of cost in the development, manufacturing and inventory management of planar ICs. Conversely, having the ability to inventory fabricated or complete circuitry which can subsequently be integrated at the IC or die level presents a opportunity for cost savings that affects all aspects of IC development and manufacturing, and extends the range of intended end use applications beyond that presently possible.